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1 LTC1750 1750f 14-bit, 80msps wide bandwidth adc n sample rate: 80msps n 500mhz full power bandwidth s/h n direct if sampling up to 500mhz n pga front end (2.25v p-p or 1.35v p-p input range) n 75.5db snr and 90db sfdr (pga = 0) n 73db snr and 90db sfdr (pga = 1) n no missing codes n single 5v supply n power dissipation: 1.45w n two pin selectable reference values n twos complement or offset binary outputs n out-of-range indicator n data ready output clock n pin-for-pin family n 48-pin tssop package n telecommunications n receivers n cellular base stations n spectrum analysis n imaging systems n mri n tomography , ltc and lt are registered trademarks of linear technology corporation. the ltc ? 1750 is an 80msps, 14-bit a/d converter de- signed for digitizing wide dynamic range signals up to frequencies of 500mhz. the input range of the adc can be optimized with the on-chip pga sample-and-hold circuit and flexible reference circuitry. the LTC1750 has a highly linear sample-and-hold circuit with a bandwidth of 500mhz. the sfdr is 82db with an input frequency of 250mhz. ultralow jitter of 0.12ps rms allows undersampling of if frequencies with minimal degradation in snr. dc specs include 3lsb inl and no missing codes. the digital interface is compatible with 5v, 3v, 2v and lvds logic systems. the enc and enc inputs may be driven differentially from pecl, gtl and other low swing logic families or from single-ended ttl or cmos. the low noise, high gain enc and enc inputs may also be driven by a sinusoidal signal without degrading performance. a separate output power supply can be operated from 0.5v to 5v, making it easy to connect directly to any low voltage dsps or fifos. the 48-pin tssop package with a flow-through pinout simplifies the board layout. 80msps, 14-bit adc with a 2.25v differential input range descriptio u features applicatio s u block diagra w of 14-bit pipelined adc 14 s/h circuit 1.125v differential analog input a in + pga a in sense v cm 4.7 f diff amp refla refhb gnd 1750 bd enc 4.7 f 1 f1 f 0.1 f 0.1 f refha reflb buffer range select 2v ref correction logic and shift register output latches control logic ov dd v dd ognd 0.5v to 5v 5v 0.1 f 1 f 1 f 1 f d13 d0 clkout enc differential encode input msbinv 0.1 f
2 LTC1750 1750f parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error (note 6) C 3 0.75 3 lsb differential linearity error l C1 0.5 1.5 lsb offset error (note 7) external reference (v sense = 1.125v, pga = 0) C35 835 mv gain error external reference (v sense = 1.125v, pga = 0) C3.5 1 3.5 %fs full-scale tempco internal reference 40 ppm/ c external reference (v sense = 1.125v) 20 ppm/ c offset tempco 20 m v/ c input referred noise (transition noise) v sense = 1.125v, pga = 0 0.92 lsb rms order part number ov dd = v dd (notes 1, 2) supply voltage (v dd ) ............................................. 5.5v analog input voltage (note 3) .... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) ..... C 0.3v to (v dd + 0.3v) digital output voltage ................. C 0.3v to (v dd + 0.3v) ognd voltage ..............................................C 0.3v to 1v power dissipation ............................................ 2000mw operating temperature range LTC1750c ............................................... 0 c to 70 c LTC1750i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c LTC1750cfw LTC1750ifw t jmax = 150 c, q ja = 35 c/w the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) absolute m axi m u m ratings w ww u package/order i n for m atio n w u u co verter characteristics u symbol parameter conditions min typ max units v in analog input range (note 8) 4.75v v dd 5.25v l 0.7 to 1.125 v i in analog input leakage current 0 < a in + , a in C < v dd l C1 1 m a c in analog input capacitance sample mode enc < enc 6.9 pf hold mode enc > enc 2.4 pf t acq sample-and-hold acquisition time l 56ns t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.12 ps rms cmrr analog input common mode rejection ratio 1.5v < (a in C = a in + ) < 3v 80 db the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sense v cm gnd a in + a in gnd v dd v dd gnd reflb refha gnd gnd refla refhb gnd v dd v dd gnd v dd gnd msbinv enc enc of ognd d13 d12 d11 ov dd d10 d9 d8 d7 ognd gnd gnd d6 d5 d4 ov dd d3 d2 d1 d0 ognd clkout pga
3 LTC1750 1750f parameter conditions min typ max units v cm output voltage i out = 0 1.95 2 2.05 v v cm output tempco i out = 0 30 ppm/ c v cm line regulation 4.75v v dd 5.25v 3 mv/v v cm output resistance 1ma ? i out ? 1ma 4 w (note 5) i ter al refere ce characteristics uu u symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input signal (pga = 0) 75.5 db 5mhz input signal (pga = 1) 73.0 db 30mhz input signal (pga = 0) 73 75.3 db 30mhz input signal (pga = 1) 72.9 db 70mhz input signal (pga = 0) 74.6 db 70mhz input signal (pga = 1) 70 72.8 db 140mhz input signal (pga = 1) 72 db 250mhz input signal (pga = 1) 70.6 db 350mhz input signal (pga = 1) 69 db sfdr spurious free dynamic range 5mhz input signal (pga = 0) 90 db 5mhz input signal (pga = 1) 90 db 30mhz input signal (pga = 0) (hd2 and hd3) 80 90 db 30mhz input signal (pga = 0) other 85 95 db 30mhz input signal (pga = 1) 90 db 70mhz input signal (pga = 0) 85 db 70mhz input signal (pga = 1) (hd2 and hd3) 80 90 db 70mhz input signal (pga = 1) other 83 95 db 140mhz input signal (pga = 1) 84 db 250mhz input signal (pga = 1) 82 db 350mhz input signal (pga = 1) 74 db s/(n + d) signal-to-(noise + distortion) ratio 5mhz input signal (pga = 0) 75.2 db 5mhz input signal (pga = 1) 72.8 db 30mhz input signal (pga = 0) 75.1 db 30mhz input signal (pga = 1) 72.6 db 70mhz input signal (pga = 0) 74.3 db 70mhz input signal (pga = 1) 72.4 db 250mhz input signal (pga = 1) 70 db thd total harmonic distortion 5mhz input signal, first 5 harmonics (pga = 0) C90 db 5mhz input signal, first 5 harmonics (pga = 1) C90 db 30mhz input signal, first 5 harmonics (pga = 0) C90 db 30mhz input signal, first 5 harmonics (pga = 1) C90 db 70mhz input signal, first 5 harmonics (pga = 0) C85 db 70mhz input signal, first 5 harmonics (pga = 1) C90 db 250mhz input signal (pga = 1) 78 db imd intermodulation distortion f in1 = 2.52mhz, f in2 = 5.2mhz (pga = 0) C 90 dbc f in1 = 2.52mhz, f in2 = 5.2mhz (pga = 1) C 90 dbc sample-and-hold bandwidth r source = 50 w 500 mhz t a = 25 c, a in = C1dbfs (note 5), v sense = v dd dy a ic accuracy u w
4 LTC1750 1750f symbol parameter conditions min typ max units t 0 enc period (note 9) l 12.5 2000 ns t 1 enc high (note 8) l 6 1000 ns t 2 enc low (note 8) l 6 1000 ns t 3 aperture delay (note 8) 0 ns t 4 enc to clkout falling c l = 10pf (note 8) l 1 2.4 4 ns t 5 enc to clkout rising c l = 10pf (note 8) t 1 + t 4 ns for 80msps 50% duty cycle c l = 10pf (note 8) l 7.25 8.65 10.25 ns t 6 enc to data delay c l = 10pf (note 8) l 2 4.9 7.2 ns t 7 enc to data delay (hold time) (note 8) l 1.4 3.4 4.7 ns t 8 enc to data delay (setup time) c l = 10pf (note 8) t 0 C t 6 ns for 80msps 50% duty cycle c l = 10pf (note 8) l 5.3 7.6 10.5 ns t 9 clkout to data delay (hold time), (note 8) l 6ns 80msps 50% duty cycle t 10 clkout to data delay (setup time), c l = 10pf (note 8) l 2.1 ns 80msps 50% duty cycle data latency 5 cycles the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w symbol parameter conditions min typ max units v dd positive supply voltage 4.75 5.25 v i dd positive supply current l 290 338 ma p dis power dissipation l 1.45 1.69 w ov dd digital output supply voltage 0.5 v dd v the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) power require e ts w u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v, msbinv and pga l 2.4 v v il low level input voltage v dd = 4.75v, msbinv and pga l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance msbinv and pga only 1.5 pf v oh high level output voltage ov dd = 4.75v i o = C10 m a 4.74 v i o = C 200 m a l 4 4.74 v v ol low level output voltage ov dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.1 0.4 v i source output source current v out = 0v C 50 ma i sink output sink current v out = 5v 50 ma the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) digital i puts a d digital outputs u u
5 LTC1750 1750f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd, they will be clamped by internal diodes. this product can handle input currents of >100ma below gnd without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 80mhz, differential enc/enc = 2v p-p 80mhz sine wave, input range = 1.125v differential, unless otherwise specified. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar offset is the offset voltage measured from C 0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. electrical characteristics typical perfor a ce characteristics uw inl dnl 8192 point fft, f in = 15.2mhz, C1db, pga = 0 8192 point fft, f in = 15.2mhz, C10db, pga = 0 8192 point fft, f in = 15.2mhz, C20db, pga = 0 8192 point fft, f in = 30.2mhz, C1db, pga = 0 output code 0 ?.5 error (lsb) ?.0 ?.0 ?.5 0 2.5 1.0 4096 8192 1750 g01 ?.5 1.5 2.0 0.5 12288 16384 output code 0 ?.0 error (lsb) 0.8 0.4 0.2 0 1.0 0.4 4096 8192 1750 g02 0.6 0.6 0.8 0.2 12288 16384 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g03 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g04 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g05 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g06 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10
6 LTC1750 1750f typical perfor a ce characteristics uw 8192 point fft, f in = 30.2mhz, C10db, pga = 0 8192 point fft, f in = 30.2mhz, C20db, pga = 0 8192 point fft, f in = 70.2mhz, C1db, pga = 0 8192 point fft, f in = 70.2mhz, C10db, pga = 0 8192 point fft, f in = 70.2mhz, C20db, pga = 0 8192 point fft, f in = 140.2mhz, C1db, pga = 1 8192 point fft, f in = 140.2mhz, C10db, pga = 1 8192 point fft, f in = 140.2mhz, C20db, pga = 1 8192 point fft, f in = 250.2mhz, C1db, pga = 1 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g07 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g08 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g09 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g10 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g11 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g12 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g13 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g14 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g15 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10
7 LTC1750 1750f typical perfor a ce characteristics uw 8192 point fft, f in = 250.2mhz, C10db, pga = 1 8192 point fft, f in = 250.2mhz, C20db, pga = 1 8192 point 2-tone fft, f in = 26.4mhz and 27.5mhz, C7db each tone, pga = 1 8192 point 2-tone fft, f in = 69.4mhz and 65.2mhz, C7db each tone, pga = 1 sfdr vs 15mhz input level input level (dbfs) ?0 sfdr (dbc and dbfs) 60 90 100 0 1750 g20 50 40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 20 120 110 80 70 30 10 sfdr vs 40.2mhz input level input level (dbfs) ?0 sfdr (dbc and dbfs) 60 90 100 0 1750 g21 50 40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 20 120 110 80 70 30 10 sfdr vs 140.2mhz input level, pga = 0 input level (dbfs) ?0 sfdr (dbc and dbfs) 60 90 100 0 1750 g22 50 40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 20 120 110 80 70 30 10 sfdr vs 250.2mhz input level, pga = 0 input level (dbfs) ?0 sfdr (dbc and dbfs) 60 90 100 0 1750 g23 50 40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 20 120 110 80 70 30 10 snr vs input frequency and amplitude, pga = 0 input frequency (mhz) 0 70 snr (dbfs) 71 72 73 74 76 50 100 150 200 1750 g24 250 300 75 ?db ?0db ?0db frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g16 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g17 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g18 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10 frequency (mhz) 0 amplitude (dbfs) ?0 ?0 ?0 40 1750 g19 ?0 ?0 ?20 10 20 30 5 15 25 35 ?00 0 ?0 ?0 ?0 ?0 ?10
8 LTC1750 1750f typical perfor a ce characteristics uw snr vs input frequency and amplitude, pga = 1 sfdr (hd2 and hd3) vs input frequency and amplitude, pga = 0 sfdr (hd2 and hd3) vs input frequency and amplitude, pga = 1 input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 200 400 500 74 1750 g25 67 100 300 71 72 73 ?db ?0db ?0db input frequency (mhz) 0 60 sfdr (dbfs) 70 80 90 100 110 50 100 150 200 1750 g26 250 300 ?db ?0db ?0db input frequency (hz) 0 50 sfdr (dbfs) 60 70 80 90 100 110 100 200 300 400 1750 g27 500 ?db ?0db ?0db sfdr and snr vs sample rate, 15.2mhz, C1db input sample rate (msps) 0 sfdr and snr (dbfs) 75 80 85 60 100 1750 g28 70 65 60 20 40 80 90 95 100 snr sfdr 120 v dd (v) 4.1 sfdr and snr (dbfs) 95 4.7 1750 g29 80 70 4.3 4.5 4.9 65 60 100 90 85 75 5.1 5.3 5.5 snr sfdr sfdr and snr vs v dd , 15.2mhz, C1db input
9 LTC1750 1750f uu u pi fu ctio s sense (pin 1): reference sense pin. gnd selects a v ref of 0.7v. v dd selects 1.125v. when v sense is between 0.7v and 1.125v, v sense is used as v ref . the adc input range is v ref /pga gain. v cm (pin 2): 2.0v output and input common mode bias. bypass to ground with 4.7 m f ceramic chip capacitor. gnd (pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): adc power ground. a in + (pin 4): positive differential analog input. a in C (pin 5): negative differential analog input. v dd (pins 7, 8, 17, 18, 20): 5v supply. bypass to agnd with 1 m f ceramic chip capacitors at pin 8 and pin 18. reflb (pin 10): adc low reference. bypass to pin 11 with 0.1 m f ceramic chip capacitor. do not connect to pin 14. refha (pin 11): adc high reference. bypass to pin 10 with 0.1 m f ceramic chip capacitor, to pin 14 with a 4.7 m f ceramic capacitor and to ground with 1 m f ceramic capacitor. refla (pin 14): adc low reference. bypass to pin 15 with 0.1 m f ceramic chip capacitor, to pin 11 with a 4.7 m f ce- ramic capacitor and to ground with 1 m f ceramic capacitor. refhb (pin 15): adc high reference. bypass to pin 14 with 0.1 m f ceramic chip capacitor. do not connect to pin 11. msbinv (pin 22): msb inversion control. low inverts the msb, 2s complement output format. high does not invert the msb, offset binary output format. enc (pin 23): encode input. the input sample starts on the positive edge. enc (pin 24): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1 m f ceramic for single-ended encode signal. pga (pin 25): programmable gain amplifier control. low selects an effective front-end gain of 1. high selects an effective gain of 1 2/3. the adc input range is v ref /pga gain. clkout (pin 26): data valid output. latch data on the rising edge of clkout. ognd (pins 27, 38, 47): output driver ground. d0-d3 (pins 28 to 31): digital outputs. ov dd (pins 32, 43): positive supply for the output driv- ers. bypass to ground with 0.1 m f ceramic chip capacitor. d4-d6 (pins 33 to 35): digital outputs. d7-d10 (pins 39 to 42): digital outputs. d11-d13 (pins 44 to 46): digital outputs. of (pin 48): over/under flow output. high when an over or under flow has occurred.
10 LTC1750 1750f ti i g diagra u ww applicatio s i for atio wu uu dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. 1750 td t 3 t 7 t 6 t 4 t 5 t 10 t 9 n t 2 t 0 t 1 t 8 data (n ?5) db13 to db0 analog input enc data clkout data (n ?4) db13 to db0 data (n ?3)
11 LTC1750 1750f applicatio s i for atio wu uu spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc equals the enc voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 p ) ? f in ? t jitter converter operation the LTC1750 is a cmos pipelined multistep converter with a front-end pga. the converter has four pipelined adc stages; a sampled analog input will result in a digitized value five cycles later, see the timing diagram section. the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmon- ics of the sample-and-hold circuit. the encode input is also differential for improved common mode noise immunity. the LTC1750 has two phases of operation, determined by the state of the differential enc/enc input pins. for brev- ity, the text will refer to enc greater than enc as enc high and enc less than enc as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. figure 1. functional block diagram diff ref amp ref buf 4.7 f 1 f 0.1 f 0.1 f 1 f internal clock signals refl refh differential input low jitter clock driver range select 2.0v reference first pipelined adc stage (5 bits) fourth pipelined adc stage (4 bits) second pipelined adc stage (4 bits) enc refha reflb refla refhb enc shift register and correction msbinv ognd of ov dd 0.5v to 5v d13 d0 clkout 1750 f01 input s/h sense v cm a in a in + pga 4.7 f third pipelined adc stage (4 bits) output drivers control logic and calibration logic
12 LTC1750 1750f in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is re- peated for the third stage, resulting in a third stage residue that is sent to the fourth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the LTC1750 cmos differential sample-and-hold. the differential ana- log inputs are sampled directly onto sampling capacitors (c sample ) through nmos switches. this direct capacitor sampling results in lowest possible noise for a given sampling capacitor size. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc/enc is low, the nmos switch connects the analog inputs to the sampling capaci- tors and they charge to, and track the differential input voltage. when enc/enc transitions from low to high the sampled input voltage is held on the sampling capacitors. during the hold phase when enc/enc is high the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc/enc transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previ- ous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve specified performance. each input should swing within the valid input range, around a common mode volt- age of 2.0v. the v cm output pin (pin 2) may be used to pro- vide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver cir- cuit. the v cm pin must be bypassed to ground close to the adc with a 4.7 m f or greater capacitor. applicatio s i for atio wu uu figure 2. equivalent input circuit c sample 3.5pf r on 30 r on 30 v dd LTC1750 a in + 1750 f02 c sample 3.5pf bias v dd 5v a in enc enc 2v 6k 2v 6k c parasitic 2.4pf c parasitic 1pf c parasitic 1pf c parasitic 2.4pf
13 LTC1750 1750f input drive circuits the LTC1750 requires differential drive for the analog inputs. a balanced input drive will minimize even order harmonics that are due to nonlinear behavior of the input drive circuits and the s/h circuit. the s/h circuit of the LTC1750 is a switched capacitor circuit (figure 2). the input drive circuitry will see a sampling glitch at the start of the sampling period, when enc/enc falls. although designed to be linear as possible, a small fraction of this glitch is nonlinear and can result in additional observed distortion if the input drive circuitry is too slow. for most practical circuits the glitch nonlinearity is more than 100db below the fundamental. the glitch will decay during the sampling period with a time constant determined by the input drive and s/h circuitry. for fast settling and wide bandwidth, a low drive imped- ance is required. the s/h bandwidth is partially deter- mined by the source impedance. the full 500mhz bandwidth is valid for source impedance (each input) less than 30 w . higher source impedance can be used but full amplitude distortion will be better with source impedance less than 100 w . transformers transformers provide a simple method for converting a single-ended signal to a differential signal; however, they have poor performance characteristics at low and high input frequencies. the lower C3db corner of rf transformers can range from tens of khz to tens of mhz. operation near this corner results in poor 2nd order harmonic performance due to nonlinear transformer core behavior. the upper C3db corner can vary from tens of mhz to several ghz. operation near the upper corner can result in poor 2nd order performance due to poor balance on the secondary. transformers should be selected to have C3db corners at least one octave away from the desired operating fre- quency. transformers with larger cores usually have better performance at lower frequency and perform better when driving heavy loads. figure 3a shows the LTC1750 being driven by an rf transformer with a center tapped secondary. the second- ary center tap is dc-biased with v cm , setting the adc input signal at its optimum dc level of 2v. in this example a 1:1 transformer is used; however, other transformer imped- ance ratios may be substituted. figure 3b shows the use of a transformer without a center tapped secondary. in this example the secondary is biased with the addition of two resistors placed in series across the secondary winding. the center tap of the secondary resistors is connected to the adc v cm output to set the dc bias. this circuit is better suited for high input frequency applications since center tapped transformers generally have less bandwidth and poor balance at high frequencies than noncenter tapped transformers. applicatio s i for atio wu uu figure 3a. single-ended to differential conversion using a transformer 1:1 25 0.1 f analog input 100 100 12pf 12pf 12pf 1750 f03 4.7 f 25 25 25 LTC1750 v cm a in + a in 1:4 10 0.1 f analog input 100 200 200 8.4pf 1750 f03b 10 25 25 8.4pf 4.7 f LTC1750 v cm a in + a in figure 3b. using a transformer without a center tapped secondary active drive circuits active circuits, open loop or closed loop, can be used to drive the adc inputs. closed-loop circuits such as op amps have excellent dc and low frequency accuracy, but have poor high frequency performance. figure 4 shows the dual lt ? 1818 op amp used for single-ended to differential
14 LTC1750 1750f signal conver sion. note that the two op amps do not have the same noise gain, which can result in poor balance at higher frequencies. the op amp configured in a gain of +1 can be configured in a noise gain of +2 with the addition of two equal valued resistors between the output and invert- ing input and between the two inputs. this however will raise the noise contributed by the op amps. reference operation figure 5 shows the LTC1750 equivalent reference circuitry consisting of a 2v bandgap reference, a 3-to-1 switch, a switch control circuit and a difference amplifier. the 2v bandgap reference serves two functions. first, it is assessable at the v cm pin to provide a dc bias point for setting the common mode voltage of any external input circuitry. second, it is used to derive internal reference levels that may be used to set the input range of the adc. an external bypass capacitor is required for the 2v refer- ence output at the v cm pin. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference, which will not be stable without this capacitor. to achieve the optimal input range for an application, the internal reference voltage (v ref ) is flexible. the reference switch shown in figure 5 connects v ref to one of two internally derived reference voltages, or to an externally derived reference voltage. the internally derived applicatio s i for atio wu uu v cm refha reflb sense tie to v dd for v ref = 1.125; tie to gnd for v ref = 0.7v; v ref = v sense for 0.7v < v sense < 1.125v 2v refla refhb 4.7 f 4.7 f internal adc high reference buffer v ref 0.1 f 1750 f05 LTC1750 4 diff amp 1 f 1 f 0.1 f internal adc low reference 2v bandgap reference 1.125v 0.7v range detect and control figure 5. equivalent reference circuit figure 4. differential drive with op amps 25 5v single-ended input 2v 1/2 range 12pf 12pf 12pf 1750 f04 4.7 f 25 100 500 500 25 25 LTC1750 + 1/2 lt1818 + 1/2 lt1818 v cm a in + a in references are selected by strapping the sense pin to gnd for 0.7v, or to v dd for 1.125v. when 0.7v > v sense > 1.125v, v sense is directly connected to v ref . because of the dual nature of the sense pin, driving it with a logic device is not recommended. reference voltages between 0.7v and 1.125v may be programmed with two external resistors as shown in figure 6a. an external reference may be used by applying its output directly or through a resistor divider to the sense pin (figure 6b). when the sense pin is driven with an externally derived reference voltage, it should be by- passed to ground as close to the device as possible with a 1 m f ceramic capacitor. a difference amplifier generates the high and low refer- ences for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins: refha and refhb for the high reference and refla and reflb for the low reference. the doubled output pins are needed to reduce package inductance. bypass capacitors must be con- nected as shown in figure 5.
15 LTC1750 1750f input range the LTC1750 performance may be optimized by adjusting the adcs input range to meet the requirements of the application. for lower input frequency applications (<80mhz), the highest input range of 1.125v (2.25v) will provide the best snr while maintaining excellent sfdr. for higher input frequencies (>80mhz), a lower input range will provide better sfdr performance with a reduc- tion in snr. the input range of the adc is determined as v ref /a pga , where v ref is the reference voltage (described in the reference operation section) and a pga is the effective applicatio s i for atio wu uu pga gain. table 1 shows the input range of the adc versus the state of the two pins, pga and sense. driving the encode inputs the noise performance of the LTC1750 can depend on the encode signal quality as much as on the analog input. the enc/enc inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 2v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.8v to v dd . each input may be driven from ground to v dd for single-ended drive. v cm sense 2v 1v 4.7 f 10k 1 f 10k 1750 f06a LTC1750 v cm sense 2v 5v 2.5k 6 4 1, 2 4.7 f 1 f 1 f 10k 0.1 f 1750 f06b LTC1750 lt1790-1.25 figure 6a. 2v range adc figure 6b. 2v range adc with external reference table 1 pga v sense input range comments 0= v dd 2.25v p-p differential best noise, snr = 75.5db. good sfdr, >82db up to 100mhz 1= v dd 1.35v p-p differential improved high frequency distortion. snr = 73db. sfdr > 80db up to 250mhz 0 = gnd 1.4v p-p differential reduced internal reference mode with pga = 0. provides similar input range as v sense = v dd and pga = 0 but with worse noise. snr = 71.4db 1 = gnd 0.84v p-p differential smallest possible input span. useful for improved distortion at very high frequencies, but with reduced noise performance. snr = 69db 0 0.7v < v sense < 1.125v 2 v sense adjustable input range with better noise performance. snr = 75.5db with peak-to-peak differential v sense = 1.125v, snr = 71.4db with v sense = 0.7v 1 0.7v < v sense < 1.125v 1.2 v sense adjustable input range with better high frequency distortion. snr = 73db with peak-to-peak differential v sense = 1.125v, snr = 69db with v sense = 0.7v
16 LTC1750 1750f maximum and minimum encode rates the maximum encode rate for the LTC1750 is 80msps. for the adc to operate properly the encode signal should have a 50% ( 4%) duty cycle. each half cycle must have at least 6ns for the adc internal circuitry to have sufficient settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. at sample rates slower than 80msps the duty cycle can vary from 50% as long as each half cycle is at least 6ns. the lower limit of the LTC1750 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on applicatio s i for atio wu uu small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the LTC1750 is 1msps. digital outputs digital output buffers figure 9 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 w to external circuitry and may eliminate the need for external damping resistors. figure 7. transformer driven enc/enc figure 8a. single-ended enc drive, not recommended for low jitter figure 8b. enc drive using a cmos-to-pecl translator v dd LTC1750 1750 f07 bias v dd 5v enc enc analog input 2v bias 2v bias 1:4 0.1 f clock input 50 6k 6k to internal adc circuits 1750 f08a enc 2v v threshold = 2v enc 0.1 f LTC1750 1750 f08b enc enc 130 3.3v 3.3v 130 d0 q0 q0 mc100lvelt22 LTC1750 83 83
17 LTC1750 1750f applicatio s i for atio wu uu output loading as with all high speed/high resolution converters the digital output loading can affect the performance. the digital outputs of the LTC1750 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 43 w on chip. lower ov dd voltages will also help reduce interference from the digital outputs. format the LTC1750 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the msbinv pin; high selects offset binary. overflow bit an overflow output bit indicates when the converter is overranged or underranged. when of outputs a logic high the converter is either overranged or underranged. output clock the adc has a delayed version of the enc input available as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal encode signal. data will be updated just after clkout falls and can be latched on the rising edge of clkout. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 3v supply then ov dd should be tied to that same 3v supply. ov dd can be powered with any voltage up to 5v. the logic outputs will swing between ognd and ov dd . grounding and bypassing the LTC1750 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. the pinout of the LTC1750 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , refha, refhb, refla and reflb pins as shown in the block diagram on the front page of this data sheet. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci- tors between refha and reflb and between refhb and LTC1750 1750 f09 ov dd v dd v dd 0.1 f 43 typical data output ognd ov dd 0.5v to v dd predriver logic data from latch figure 9. equivalent circuit for a digital output buffer
18 LTC1750 1750f refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recomended. the large 4.7 m f capacitor between refha and refla can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC1750 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. an analog ground plane separate from the digital process- ing system ground should be used. all adc ground pins labeled gnd should connect to this plane. all adc v dd bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. the LTC1750 has three output driver ground pins, labeled ognd (pins 27, 38 and 47). these grounds should con- nect to the digital processing system ground. the output driver supply, ov dd should be connected to the digital processing system supply. ov dd bypass capacitors should bypass to the digital system ground. the digital process- ing system ground should be connected to the analog plane at adc ognd (pin 38). heat transfer most of the heat generated by the LTC1750 is transferred from the die through the package leads onto the printed circuit board. in particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. these pins have the lowest thermal resistance between the die and the outside envi- ronment. it is critical that all ground pins are connected to a ground plane of sufficient area. the layout of the evalu- ation circuit shown on the following pages has a low ther- mal resistance path to the internal ground plane by using multiple vias near the ground pins. a ground plane of this size results in a thermal resistance from the die to ambient of 35 c/w. smaller area ground planes or poorly connected ground pins will result in higher thermal resistance. applicatio s i for atio wu uu
19 LTC1750 1750f package descriptio u fw package 48-lead plastic tssop (6.1mm) (reference ltc dwg # 05-08-1651) fw48 tssop 0502 0.09 ?0.20 (.0035 ?.008) 0 ?8 0.45 ?0.75 (.018 ?.029) 0.17 ?0.27 (.0067 ?.0106) 0.50 (.0197) bsc 6.0 ?6.2** (.236 ?.244) 7.9 ?8.3 (.311 ?.327) 134 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 12.4 ?12.6* (.488 ?.496) 1.20 (.0473) max 0.05 ?0.15 (.002 ?.006) 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 47 c .10 -t- -c- millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale * ** 0.32 0.05 0.50 typ 6.2 0.10 8.1 0.10 recommended solder pad layout 0.95 0.10 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC1750 1750f ? linear technology corporation 2004 lt/tp 0204 1k ? printed in the usa part number description comments ltc1405 12-bit, 5msps sampling adc with parallel output pin compatible with the ltc1420 ltc1406 8-bit, 20msps adc undersampling capability up to 70mhz ltc1411 14-bit, 2.5msps adc 5v, no pipeline delay, 80db sinad ltc1412 12-bit, 3msps, sampling adc 5v, no pipeline delay, 72db sinad ltc1414 14-bit, 2.2msps adc 5v, 81db sinad and 95db sfdr ltc1420 12-bit, 10msps adc 71db sinad and 83db sfdr at nyquist lt ? 1461 micropower precision series reference 0.04% max initial accuracy, 3ppm/ c drift ltc1666 12-bit, 50msps dac pin compatible with the ltc1668, ltc1667 ltc1667 14-bit, 50msps dac pin compatible with the ltc1668, ltc1666 ltc1668 16-bit, 50msps dac 16-bit monotonic, 87db sfdr, 5pv-s glitch impulse ltc1741 12-bit, 65msps adc pin compatible with the ltc1743, ltc1745, ltc1747 ltc1742 14-bit, 65msps adc pin compatible with the ltc1744, ltc1746, ltc1748 ltc1743 12-bit, 50msps adc pin compatible with the ltc1741, ltc1745, ltc1747 ltc1744 14-bit, 50msps adc pin compatible with the ltc1742, ltc1746, ltc1748 ltc1745 12-bit, 25msps adc pin compatible with the ltc1741, ltc1743, ltc1747 ltc1746 14-bit, 25msps adc pin compatible with the ltc1742, ltc1744, ltc1748 ltc1747 12-bit, 80msps adc pin compatible with the ltc1741, ltc1743, ltc1745 ltc1748 14-bit, 80msps adc pin compatible with the ltc1742, ltc1744, ltc1746 ltc1749 12-bit, 80msps adc with wide bandwidth pin compatible with the LTC1750 lt1807 325mhz, low distortion dual op amp rail-to-rail input and output lt5512 high signal level down converting mixer dc to 3ghz, 17dbm iip3, integrated lo buffer lt5515 direct conversion demodulator 1.5ghz to 2.5ghz, 21.5dbm iip3, integrated lo quadrature generator lt5516 direct conversion quadrature demodulator 800mhz to 3ghz, 17dbm iip3, integrated lo buffer lt5522 high signal level down converting mixer 600mhz to 3ghz, 25dbm iip3, integrated lo buffer related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com

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